1. Field of the Invention
Semiconductor integrated circuit devices having MOS transistors are used widely in electronic equipment such as personal computer, a cellular phone, or a home electric apparatus. In semiconductor devices used for the electronic equipment, a power supply voltage has been decreasing year after year for the semiconductor device used in a signal processing system such as an LSI or a CPU. On the other hand, the power supply voltage of the semiconductor device used for controlling the power supply voltage, a driving system, a peripheral equipment, etc. has not decreased. Therefore, a semiconductor device high in withstand voltage is required. The present invention relates to the semiconductor device integrating the MOS transistor having the high withstand voltage.
2. Description of the Related Art
MOS transistors high in withstand voltage, which are used for the semiconductor device employ an LDD (lightly doped drain) structure, a DDD (double doped drain) structure, a drain structure having a low concentration drift region utilizing a field dope, and the like. These structures make it possible to relax an electric field generated in the vicinity of a drain, so that the withstand voltage of the drain can be increased. However, the above-mentioned MOS transistors each have the low concentration drift region and thus, a parasitic resistance is large and it is impossible to cause a large amount of current to flow therethrough. Also, in a case where excess charges are forcibly caused to flow in a low concentration drain region due to static electricity etc., the region involves such a problem that heat is excessively generated and the current concentratedly flows in a part, so that it is easily subjected to breakdown. In particular, in an N-channel MOS transistor, when the excess charges are applied to the drain, an NPN bipolar transistor is turned ON, which is parasitically formed among the drain, a well, and a source arranged in the stated order. This causes a current of several hundreds of mA or more to flow therethrough, so that the low concentration drain region is easily subjected to breakdown.
Therefore, as shown in FIG. 4, for example, a structure is employed such that the drain region is formed by diffusing an impurity deeply to thereby increase a volume of the low concentration drain region, so that density of the current flowing in the drain is lowered to enhance a resistance to an excess current.
However, in a case where the drain region is formed through the deep diffusion in order to increase a volume of the drain region, a difference is small between diffusion depth of the drain region and that of the well region. Thus, there arises a problem such that the withstand voltage among the drain, the well, and the semiconductor substrate is decreased. In the case of the N-channel MOS transistor, when the semiconductor substrate is a P-type, the well and the semiconductor substrate have the same electric polarity. Thus, there causes no problem regarding the decreased withstand voltage among the drain, the well, and the semiconductor substrate. However, when the semiconductor substrate is an N-type, the NPN bipolar transistor is parasitically formed among the drain, the well, and the semiconductor substrate. At this time, the well region serving as a base of the NPN bipolar transistor is high in resistance and a distance between a lower end of the drain region and the semiconductor substrate, which corresponds to a base width of the NPN bipolar transistor is small. Therefore, the parasitic NPN bipolar transistor is caused to operate at a relatively low voltage and the drain cannot secure a sufficient withstand voltage.
Also, when the semiconductor substrate is an N-type, a state in which a depletion layer formed in a portion below the drain and spread between the drain and the well and a delpletion layer spread between the well and the semiconductor substrate are communicated with each other, i.e., punch-through involves a leak current, which causes the withstand voltage of the drain to decrease. An impurity concentration is low in a portion below the well, so that the depletion layers spread between the drain and the well and between the well and the semiconductor substrate are both expanded up to several microns. Thus, a problem regarding the punch-through is serious.
In order to solve the above-mentioned problem, the following is considerable: the well region is formed such that the diffusion depth thereof is sufficiently larger than that of the drain region. For this purpose, there is provided a method in which a drive-in process for forming the well region is performed at high temperature for a long period of time, a method in which an impurity implantation amount necessary for forming the well region is increased, a method in which ion implantation for implanting the impurity is performed at high energy, or the like. However, these methods involve a problem in terms of production in that productivity is decreased due to an increased process time, a special manufacturing apparatus is required, or the like. In addition, there arises a problem in that the impurity concentration in the surface of the well, which largely affects characteristics of the MOS transistor, becomes high to lower controllability.